Solid state and non-volatile memories are known in the art. Flash memory is one type of non-volatile memory. FIG. 1 illustrates a block diagram of a flash memory device. The flash memory 100 includes a memory cell array 116, data latch 118, sense amp 114, X-decoder 120, Y-decoder 122, a control logic circuit 110, and input/output buffer 112.
The operation of flash memories is well known and therefore is only briefly described herein. In one type of memory control interface, an external controller initiates a memory operation by asserting a chip enable signal (CE) and supplying address signals A0-AN (corresponding to 2.sup.N+1 memory locations) designating the address of a memory location where the operation is to be performed. If the memory operation is a program operation, the data to be programmed is provided to the addressed memory location via the bidirectional data lines D0-DK (corresponding to K+1 bit memory words). If the memory operation is a read operation, the stored information is read out from the same bidirectional data lines D0-DK. The memory 100 also provides connections for an external power supply VCC and ground (GND).
The heart of the memory 100 is cell array 116, which consists of flash memory cells. Each cell is capable of storing one bit of data, arranged in rows and columns. In the conventional manner, all of the control gates of the cells in one row are energized for a memory operation (either a read or a program) by a word line uniquely associated with that row. Typically, in a flash memory, program operations are performed a page at a time, read operations read individual bytes or words, and erase operations are performed a sector at a time. A memory operation cannot be performed unless the word line associated with the target row of cells is activated.
At least a subset of the cells in a row (typically all of the cells that store data for one memory word or byte) can be accessed simultaneously for a given memory operation via the sub-bit lines, also referred to as divided bit lines. When the memory operation is a read, the sub-bit lines are coupled to sense amplifiers that "sense" the data stored in the corresponding cells of the row whose word line is active. When the memory operation is a program operation the sub-bit lines carry the signals used to program the corresponding cells of the row associated with the active word line.
The control logic circuit 110 controls the other blocks of memory 100. Depending on the operation to be performed, the control logic issues the appropriate signals to address latch 124, data latch 118, sense amp 114 or input/output buffer 112. For the erase operation a subset of the address signals are also used to select the sector to erase.
Regardless of whether the memory operation is a read or a program, X-decoder 120 decodes the X address signal component of address signals A0-AN and activates the word line of the row that includes the memory word that is accessed in the current memory operation.
If the operation is a program operation, the input/output buffer 112 buffers the input data signals D0-DK and loads the buffered data via the bi-directional data bus to data latch 118. The data is then coupled to the sub-bit lines to program the cells comprising the word whose word line was activated for the current operation by X-decoder 120.
If the operation is a read, sense amplifiers sense the signals on the respective sub-bit lines, convert the sensed signals into binary (e.g. high or low) voltages that represent the programmed state of the addressed word and output the word's bit values to the I/O data circuit via the bi-directional bus. The output data are latched into data latch 118 and then buffered by the input/output buffer 112.
An individual flash memory cell includes a metal-oxide-semiconductor ("MOS") device having spaced-apart drain and source regions fabricated on a substrate and defining a channel region therebetween. A very thin gate oxide layer overlies the channel region, and a floating charge-retaining storage gate overlies the oxide layer. A control gate at least partially overlies the floating gate and is insulated therefrom.
In practice, a plurality of such memory cells are arrayed in addressable rows and columns to form a flash memory array. Individual cells in the array are accessed for purposes of programming, reading or erasing data by decoding row and column address information.
FIG. 2 illustrates a circuit diagram of a conventional memory sector 200 in a non-volatile memory device. A small section of the memory array comprising two main bit lines (MBLs) 210 and 211 is shown for simplicity. Similarly, only a small number of the memory array rows are illustrated. Each main bit line spans the full height of the memory array, and one main bit line typically spans many sectors stacked along the main bit line. Each main bit line has two sub-bit lines (SBLs) in each sector associated with it. Each sub-bit line is coupled to a main bit line via one of the select transistors 231-234. For example, MBL 210 is coupled to the drain of select transistor 231, and the source of transistor 231 is coupled to SBL 221. At the end of each main bit line is a column latch. The column latches 236 and 238 store program data in program mode operation. Typically the column latches for adjacent main bit lines are placed at opposite ends of the main bit lines, as illustrated in FIG. 2. Alternating the location of the column latches facilitates compact layout of the memory array.
The core of the memory array is the memory cell transistors. The memory cell transistors are represented by a transistor symbol with one additional line, added parallel to the line representing the transistor gate, for example, transistors 261-264 are memory cell transistors. The memory cell transistors have a floating gate and indicate a logic bit based on the charge stored on the floating gate.
Typically, the control gates for a group of cells in a given row are formed from a continuous strip of conductive material that defines a so-called word line, abbreviated "WL." A word line might comprise, for example, a group of eight cells that collectively store one byte, or sixteen cells that store one word. For a given column in the array, the drain leads of all cells in the column are coupled to a sub-bit line within the same sector.
Within the memory array, an individual cell is addressed and thus selected for reading or programming (writing) by specifying its row (or word line), and its column (or sub-bit line). Erase operations are performed a sector at a time. A 2 Mbit memory, for example, may comprise an array of 2048.times.1024 bits, in which there are 2048 word lines and 1024 sub-bit lines. Commonly, blocks of memory cells are collectively grouped into sectors. Cell addressing is accomplished by coupling address bits to precoding X-decoders and to precoding Y-decoders who respectively select the addressed word line and sub-bit lines in the array.
Programming an addressed MOS memory cell occurs in a program mode using Fowler-Nordheim ("FN") tunneling. Electrons tunnel from the floating gate through the thin gate oxide. The control gate-source threshold voltage required before substantial MOS device drain-source current occurs is affected by the amount of such charge retained on the floating gate. Thus, storage cell programming removes negative charge from the floating storage gate, and the amount of charge on the floating gate causes the cell to indicate storage of either a logic "1" or "0" in a read-out mode.
The above-described storage cells are non-volatile in that the charge on the storage gate, and thus the "0" or "1" bit stored in the cell, remains even when control and operating voltages to the array are turned off. In Fowler-Nordheim tunneling type devices, in the program (write) mode, the control gate is coupled to a large negative potential of perhaps -10 V, the drain is coupled to perhaps +5 V, the source floats, and the substrate is grounded (meaning that it is coupled to the circuit ground node). This causes electrons to be removed from the floating gate by tunneling. The drain is coupled to a voltage supply through the selected sub-bit line. Therefore the supply voltage is also applied to the other cells coupled to the selected sub-bit line. One problem with conventional cell arrays is that the drain voltage can disturb the charge in the floating gates of the other cells coupled to the selected sub-bit line. This is called drain disturb.
Another problem with conventional cell arrays is that the large program voltages required to induce electron tunneling from the floating gate can cause significant voltage levels to be capacitively coupled to adjacent unselected sub-bit lines. This coupling of voltages is referred to as program disturb. In the conventional page program memory array of FIG. 2 an unselected sub-bit line always has a selected sub-bit line on either side of it. For example, in a page program operation if control line 240 is selected, then select transistors 231, 233 and the other select transistors coupled to control line 240 are all turned on. As a result SBL 221, 223 and the subsequent odd numbered SBLs are selected. Having selected sub-bit lines on both sides of unselected sub-bit lines can cause significant program disturb coupling levels.
In a read mode, the charge stored on the floating gate of an addressed MOS memory cell may be read by coupling a voltage approximately equal to Vcc to the control gate, and reading the drain-to-source current. The presence or absence of charge on the stored gate defines a binary "1" or "0" bit that is read-out from the addressed memory cell by a sense amplifier coupled to the bit line.
In an erase mode, the electrons trapped on the floating gates of a group of addressed MOS memory cells are encouraged to flow by electron tunneling to the floating gate. During this erase mode, a group of word line decoders cause the addressed cells' control gates to be coupled to +10 V, the sources and substrates to be coupled to perhaps -8 V and the drains to float. The electrons are thereby encouraged to flow by electron tunneling to the floating gate. In flash memory devices erase operations are typically performed on an entire sector at a time.
Thus an improved non-volatile memory device that overcomes the program disturb, drain disturb and other problems of the prior art would be highly desirable.